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HYUNDAI MicroElectronics
GMS81504
GMS81504 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
OVERVIEW Description
The GMS81504 is a high-performance CMOS 8-bit microcontroller with 4K bytes of ROM. The device is one of GMS800 family. The HYUNDAI GMS81504 is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS81504 provides the following standard features: 4K bytes of ROM, 128 bytes of RAM, 23 I/O lines(21 lines for 28SOP), 16-bit or 8-bit timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry. In addition, the GMS81504 supports power saving modes to reduce power consumption. The Stop Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset or external interrupt.
ROM size 4K bytes 4K bytes (OTP) RAM size 128 bytes 128 bytes Package 30SDIP 28SOP 30SDIP Device name GMS81504 K GMS81504 D GMS81504T K
Features
4K On-chip Program Memory 128 Bytes of On-Chip Data RAM Instruction execution time: 0.5us at 8MHz 2.7V to 5.5V Wide Operating Range 1~8 MHz Operating frequency Basic Interval Timer Two 8-Bit Timer/ Counters (can be used as one 16-bit) Two external interrupt ports One Programmable Clock Out port One Buzzer Driving port 23 Programmable I/O Lines Seven Interrupt Sources All LED Direct Drive Output Ports 4-Channel 8-Bit On-Chip Analog to Digital Converter Power Down Mode (STOP Mode)
Development Tools
The GMS800 family is supported by a full-featured macro assembler, an in-circuit emulators CHOICEJr.TM, socket adapters for OTP device. The availability of OTP devices are especially useful for customers expecting frequent code changes and updates. The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration fuses must be programmed.
In-Circuit Emulators OTP devices Socket Adapters for OTP Devices Assembler CHOICE-Jr.TM GMS81504T K (30 SDIP) OA815A-30SD (30 SDIP)
HME Macro Assembler
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GMS81504
HYUNDAI MicroElectronics
BLOCK DIAGRAM
RAM 128 x 8 BIT* TIMER 0 TIMER 1 ROM 4K x 8 CPU BUZZER ADC EXT INT
PORT 0
8
I/O
R00~R07
PORT 4
8
I/O
R40~R47 R55/BUZ R56** R57** R64 R65 R66 R67
PORT 5
PORT 6
* BIT: Basic Interval Timer ** The R56, R57 port are not served on 28SOP package.
Figure 1. Block Diagram
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HYUNDAI MicroElectronics
GMS81504
PIN ASSIGNMENT
30 SDIP
28 SOP
Figure 2. Pin Connections
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GMS81504
HYUNDAI MicroElectronics
PACKAGES
Unit: INCH
30 SDIP
28 SOP
0.299 0.419 0.292 0.398
0.713 0.697 0.106 0.093 0.020 0.013 0.050 BSC 0.0118 0.004
0~8
0.042 0.016
0.0125 0.008
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GMS81504 R55, R56, R57: R5 is a 3-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R5 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R56 and R57 differs in having internal pull-ups. Port R55 serves the functions of special features.
Port Pin R55 Alternate Function BUZ (Square wave output for Buzzer driving)
PIN DESCRIPTIONS
VDD: Supply voltage. VSS: Circuit Ground. TEST: For test purposes only. Connect it to VDD. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R0 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R40~R47: R4 is an 8-bit, CMOS, bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R4 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. In addition, Port R40, R41, R44, R46 serve the functions of the various following special features.
Port Pin R40 R41 R44/EC0 R46 Alternate Function INT0 (External Interrupt 0) INT1 (External Interrupt 1) EC0 (External Count Input to Timer/Counter 0) T1O (Timer 1 Clock-Out)
R64~R67: R6 is an 4-bit, CMOS, bidirectional I/O port. R64~R67 are bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. R64~R67 pins that have 1 or 0 written to their Port Direction Mode Register, can be used as outputs or inputs. R6 serves the analog to digital converter functions of following.
Port Pin R64 R65 R66 R67 Alternate Function AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7)
AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source.
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GMS81504
Descriptions Primary Functions VDD VSS AVDD TEST RESET XIN XOUT R00~R07 R40/INT0 R41/INT1 R42 R43 R44/EC0 R45 R46/T1O R47 R55/BUZ R56 1) R57 1) R64/AN4 R65/AN5 R66/AN6 R67/AN7 I I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power supply to MCU Ground Power supply for ADC Test mode Reset the MCU Oscillation input Oscillation output General I/O General I/O " " " " " " " General I/O " " General I/O " " " Secondary Functions External interrupt 0 External interrupt 1 External count input 0 Timer 1 output Buzzer driving output Analog input 4 Analog input 5 Analog input 6 Analog input 7
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Port Pin
I/O
Pull-up/ Pull-down Pull-up -
RESET Low Oscillation Oscillation Input 3)
STOP Mode Last state Low High Last state
Input 3) -
Last state
Pull-up 2) Pull-up 2)
Input 3)
Last state
Input 3) -
Last state
NOTES: 1) R56 and R57 are not physically served on 28 pin SOP package. 2) When input mode is selected, pull-up is activated. In output mode, pull-up is de-activated. 3) During MCU reset, status of R56,R57 are weak high (Typ. impedance 50~100K). Other pin impedance is very high(High-Z).
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GMS81504
PORT STRUCTURES
R00~R07, R47
DATA REG. DATA BUS VDD PROTECT DIODE
DIRECTION REG. DATA BUS PROTECT DIODE VSS DATA BUS MUX
Rd.
R40/INT0, R41/INT1, R44/EC0
PMR4 DATA REG. DATA BUS DIRECTION REG. DATA BUS
DATA BUS
MUX
Rd. ALTERNATE FUNCTION EX) INT0
R46/T1O, R55/BUZ
SELECTION (PMR) ALTERNATE FUNCTION EX) T1O DATA REG. DATA BUS DATA BUS DIRECTION REG. DATA BUS MUX MUX
Rd.
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R42, R43, R45
DATA REG. DATA BUS VDD PROTECT DIODE
DIRECTION REG. DATA BUS PROTECT DIODE VSS DATA BUS MUX
Rd.
R56, R57
DATA REG. DATA BUS PULL-UP RESISTOR
DIRECTION REG. DATA BUS
DATA BUS
MUX
Rd.
INPUT MODE: PULL-UP RESISTOR IS ACTIVATED. OUTPUT MODE: PULL-UP RESISTOR IS DE-ACTIVATED.
R64/AN4, R65/AN5, R66/AN6, R67/AN7
DATA REG. DATA BUS DIRECTION REG. DATA BUS
DATA BUS Rd. TO A/D Converter
MUX Rd.
0: Output 1: Reset, Input, AD ch. select
Ch. Select
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GMS81504
RESET
TEST
Pull-up Resister
OTP: No P-Ch diode
XIN, XOUT
VDD VDD XIN
VDD XOUT
STOP
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HYUNDAI MicroElectronics
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . -0.3 to +6.0 V Storage Temperature . . . . . . . . . . . . -40 to +125 C Voltage on any pin with respect to Ground (VSS) . . . . . . -0.3 to VDD+0.3 V Maximum current out of VSS pin . . . . . . . . . 150 mA Maximum current into VDD pin . . . . . . . . . 100 mA Maximum output current sunk by (IOL per I/O Pin) R00~R07, R42, R43, R56, R57 . . . . . . . . 30 mA R40, R41, R44~R47, R55, R64~67 . . . . . . 20 mA Maximum output current sourced by (IOH per I/O Pin) R00~R07, R42, R43, R56, R57 . . . . . . . . 24 mA R40, R41, R44~R47, R55, R64~67 . . . . . . 18 mA Maximum current ( IOL) . . . . . . . . . . . . 120 mA Maximum current ( IOH) . . . . . . . . . . . . 100 mA Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these of any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply Voltage Operating Frequency Operating Temperature Symbol VDD fXIN TOPR Condition fXIN = 8 MHz fXIN = 4 MHz VDD = 4.5~5.5V VDD = 2.7~5.5V Specifications Min. 4.5 2.7 1.0 1.0 -20 Max. 5.5 5.5 8.0 4.2 80 V MHz C Unit
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GMS81504
DC Characteristics ( 5V )
(VDD = 5.0V 10%, VSS = 0V, TA = -20 ~ 80 C, fXIN = 8 MHz) Parameter XIN Input High Voltage RESET, R0, R4, R5, R6 XIN Input Low Voltage RESET, R0, R4, R5, R6 R0, R4, R5, R6 R40, R41, R44~R47, R55, R6 R0, R42, R43, R56, R57 Input Leakage Current Input Pull-up Current Power Current Hysteresis RESET, R0, R4, R5, R6 RESET R56, R57 Operating mode STOP mode RESET, R40~R45 Pin Symbol VIH1 V IH2 VIL1 VIL2 VOH VOL1 VOL2 IIH IIL IP1 IP2 IDD ISTOP V T+ ~VTTest Condition VDD = 5V IOH = -2mA VDD = 5V IOL = 5mA VDD = 5V IOL = 10mA VI = VDD VI = 0V VDD = 5V VDD = 5V fXIN=8MHz VDD = 5V VDD = 5V Specifications Min. 0.9VDD 0.8VDD 0 0 Typ.* Max. VDD VDD 0.1VDD 0.2VDD 1.0 1.0 5.0 5.0 -30 -15 40 30 V V V V V V V uA uA uA uA mA uA V Unit
Output High Voltage
V DD-1.0 VDD-0.2 -5.0 -5.0 -180 -90 0.5 0.3 0.6 -120 -60 5 2 0.8
Output Low Voltage
* : Data in "Typ" column is at 5 V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
A/D Converter Characteristics ( 5V )
(VDD = 5.0V 10%, VAIN = 5.0V, VSS = 0V, TA = 25 C) Parameter Analog Input Range Overall Accuracy Conversion Time Analog power supply Input Range Symbol Min. VAIN ACC TCONV VAVDD VSS 4.5 Specifications Typ.* 2.0 5.0 Max. AVDD 3.0 40 5.5 V LSB uS V Unit
* : Data in "Typ" column is at 5 V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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DC Characteristics ( 3V )
(VDD = 3.0V 10%, VSS = 0V, TA = -20 ~ 80 C, fXIN = 4 MHz) Parameter XIN Input High Voltage RESET, R0, R4, R5, R6 XIN Input Low Voltage RESET, R0, R4, R5, R6 R0, R4, R5, R6 R40, R41, R44~R47, R55, R6 R0, R42, R43, R56, R57 Input Leakage Current Input Pull-up Current Power Current Hysteresis RESET, R0, R4, R5, R6 RESET R56, R57 Operating mode STOP mode RESET, R40~R45 Pin Symbol VIH1 V IH2 VIL1 VIL2 VOH VOL1 VOL2 IIH IIL IP1 IP2 IDD ISTOP V T+ ~VTTest Condition VDD = 3V IOH = -2mA VDD = 3V IOL =2mA VDD = 3V IOL = 5mA VI = VDD VI = 0V VDD = 3V VDD = 3V fXIN=4MHz VDD = 3V VDD = 3V -3.0 -3.0 -15 -7.5 0.3 Specifications Min. 0.9VDD 0.8VDD 0 0 Typ.* Max. VDD VDD 0.1VDD 0.2VDD 1.0 1.0 3.0 3.0 -60 -30 5 10 V V V V V V V uA uA uA uA mA uA V Unit
Output High Voltage
VDD -1.0 VDD-0.4 0.3 0.4 -30 -15 1 1 0.6
Output Low Voltage
* : Data in "Typ" column is at 3 V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. **: Power Fail Detection function is not available.
A/D Converter Characteristics ( 3V )
(VDD = 3.0V 10%, VAIN = 3.0V, VSS = 0V, TA = 25 C) Parameter Analog Input Range Overall Accuracy Conversion Time Analog power supply Input Range Symbol Min. V AIN ACC TCONV VAVDD VSS 2.7 Specifications Typ.* 1.5 3.0 Max. AVDD 2.5 40 3.3 V LSB uS V Unit
* : Data in "Typ" column is at 3 V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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GMS81504
AC Characteristics
(VDD = 2.7~5.5V, VSS = 0V, TA = -20 ~ 80 C) Parameter Main clock frequency Oscillation stabilization Time External Clock Pulse Width External Clock Transition Time Interrupt Pulse Width RESET Input Low Width Event Counter Input Pulse Width Event Counter Transition Time XIN XIN, XOUT XIN XIN INT0, INT1 RESET EC0 EC0 Pin Symbol Min. fXIN tST tCPW tRCP, tFCP tIW tRST tECW tREC, tFEC 1 20 80 2 8 2 Specifications Typ. Max. 8 20 20 MHz ms ns ns tSYS tSYS tSYS ns Unit
Timing Chart
1 / fOSC
tCPW
tCPW 0.9VDD 0.1VDD
XIN
tRCP tFCP
tIW
tIW
INT0, INT1
0.8VDD 0.2VDD
tRST
RESET
0.2VDD
tECW
tECW
EC0
0.8VDD 0.2VDD tREC tFEC
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TYPICAL CHARACTERISTICS
These parameters are for design guidance only and are not tested.
IDD - VDD
TA=25C fXIN = 8MHz
IDD (mA) 8 6 4
ISTOP (uA) 8 6 4
ISTOP
TA=25C
fXIN = 4MHz 2 2
0
2
3
4
5
VDD (V)
0
2
3
4
5
VDD (V)
VDD=5V
IOL (mA) 24 18 12 6 VOL (V)
IOL - VOL
VDD=5.0V TA=25C
IOL (mA) 20 15 10 5
IOL - VOL
VDD=5.0V TA=25C
0
1
2
3
4
0
1
2
3
4
VOL (V)
R00~R07, R42, R43, R56, R57
R40, R41, R44~R47, R55, R64~67
IOH (mA) -24 -18 -12 -6
IOH - VOH
VDD=5.0V TA=25C
IOH (mA) -20 -15 -10 -5 4 VDD-VOH (V)
IOH - VOH
VDD=5.0V TA=25C
0
1
2
3
0
1
2
3
4 VDD-VOH (V)
R00~R07, R42, R43, R56, R57
R40, R41, R44~R47, R55, R64~67
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GMS81504
VDD=3.0V
IOL (mA) 20 15 10 5
IOL - VOL
VDD=3.0V TA=25C
IOL (mA) 8 6 4 2
IOL - VOL
VDD=3.0V TA=25C
0
0.5
1.0
1.5
2.0
2.5 (V) VOL
0
0.5
1.0
1.5
2.0
2.5 (V)
VOL
R00~R07, R42, R43, R56, R57
R40, R41, R44~R47, R55, R64~67
IOH (mA) -8 -6 -4 -2
IOH - VOH
VDD=3.0V TA=25C
IOH (mA) -8 -6 -4 -2
IOH - VOH
VDD=3.0V TA=25C
0
0.5
1.0
1.5
2.0
2.5 (V) VDD -- VOH --
0
0.5
1.0
1.5
2.0
2.5 (V) VDD -- VOH --
R00~R07, R42, R43, R56, R57
R40, R41, R44~R47, R55, R64~67
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GMS81504
HYUNDAI MicroElectronics The index registers also have increment, decrement, compare and data transfer functions and they can be used as simple accumulators. Stack Pointer: The stack pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. The stack can be located at any position within 00H to 7FH of the internal data memory.
Caution: The stack pointer must be initialized by software because its value is undefined after reset. Ex) LDX #07FH TXSP ; SP 7FH
MEMORY ORGANIZATION
The GMS81504 has separate address spaces for Program and Data Memory. Program memory can only be read, not written to. It can be up to 4K bytes of Program Memory. Data memory can be read and written to up to 128 bytes including the stack area.
Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two Index registers (X,Y), the Stack Pointer (SP) and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW
ACCUMULATOR X REGISTER Y REGISTER
Stack Address (00H~7FH) 15 0 87 SP 0
Hardware fixed. STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD
Figure 5. Stack Pointer
Caution: To prevent overrapped between user RAM an system stack area, user have to consider using RAM.
Figure 3. Configuration of Registers Accumulator: The accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving and conditional judgment, etc. The accumulator can be used as a 16-bit register with Y register as shown below.
Y Y A TWO 8-BIT REGISTERS ONE "YA" 16-BIT REGISTER A
Reset Routine Example:
RESET: CLR_LP: ORG LDX LDA STA CMPX BNE LDX TXSP : 0F000H #0 #0 {X}+ #80H CLR_LP #07FH
;RAM CLEAR
;INITIALIZE SP.
Figure 4. Configuration of YA 16-bit register X register, Y register: In the addressing modes which use these index registers, the register contents are added to the specified address and this becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables.
Program Counter: The program counter is a 16-bit wide which consists of two 8-bit registers, PCH, PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset vector address (PCH: FFH, PCL: FEH). . Program Status Word : The Program Status Word (PSW) contains several status bits that reflect the current state of the CPU. The PSW shown in Figure 6. It contains the Negative flag, the Overflow flag, the Direct page flag, the Break flag, the Half Carry (for BCD operations), the Interrupt enable flag, the Zero
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GMS81504
MSB
LSB V G B H I Z C RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERANDS
PSW
NEGATIVE FLAG
N
OVERFLOW FLAG G FLAG TO SELECT DIRECT PAGE (NOT AVAILABLE ON GMS81504) BRK FLAG
Figure 6. PSW (Program Status Word) Register flag and the Carry bit. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift instruction or rotate instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction, cleared by the DI instruction. [Half carry flag H] After operation, set when there is a carry from bit 3 of ALU or there is not a borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction, clearing with Overflow flag (V). [Break flag B] This flag set by software BRK instruction to distinguish BRK from TCALL instruction which as the same vector address. [Direct page flag G] This flag is not available on GMS81504 because this flag is usable over 256 bytes RAM other than the GMS81504, assign direct page for direct addressing mode. In the direct addressing mode, addressing area is within zero page 00H to FFH when this flag is "0". If it is set to "1", addressing area is 100H to 1FFH. It is set by SETG instruction, and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs in the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, for other than the above, bit 6 of memory is copy to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copy to this flag.
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1) INTERRUPT
M(SP) (PCH) SP SP - 1 M(SP) (PCL) SP SP - 1 M(SP) (PSW) SP SP - 1
2) RETI
SP SP + 1 (PSW) M(SP) SP SP + 1 (PCL) M(SP) SP SP + 1 (PCH) M(SP)
3) CALL
M(SP) (PCH) SP SP - 1 M(SP) (PCL) SP SP - 1
4) RET
SP SP + 1 (PCL) M(SP) SP SP + 1 (PCH) M(SP)
5) PUSH A (X,Y,PSW)
M(SP) ACC. SP SP - 1
6) POP A (X,Y,PSW)
SP SP + 1 M(SP) (PCH)
Figure 7. Stack Operation
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GMS81504
Address FFC0H FFC2H FFC4H FFC6H FFC8H FFCAH FFCCH FFCEH FFD0H FFD2H FFD4H FFD6H FFD8H FFDAH FFDCH FFDEH TCALL Name TCALL15 TCALL14 TCALL13 TCALL12 TCALL11 TCALL10 TCALL9 TCALL8 TCALL7 TCALL6 TCALL5 TCALL4 TCALL3 TCALL2 TCALL1 TCALL0/ BRK1)
Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this devices have 4K bytes (8K for GMS81608) program memory space only the physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8, shows a map of the upper part of the Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH, FFFFH. As shown in Figure 8, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program, Page Call (PCALL) area contains subroutine program, to reduce program byte length because of using by 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, more useful to save program byte length.
1) The BRK software interrupt is using same address with TCALL0.
F000H PROGRAM MEMORY FEFFH FF00H FFBFH FFC0H
The interrupt causes the CPU to jump to specific location, where it commences execution of the service routine. The External interrupt 0, for example, is assigned to location FFFAH. The interrupt service locations are spaced at 2-byte interval : FFF8H for External Interrupt 1, FFFAH for External Interrupt 0, etc. Any area from FF00H to FFFFH, if it not going to be used, its service location is available as general purpose Program Memory.
Address FFE0H FFE2H FFE4H FFE6H FFE8H FFEAH FFECH FFEEH FFF0H FFF2H FFF4H FFF6H FFF8H FFFAH FFFCH FFFEH Vector Name Basic Interval Timer Analog to Digital Converter Timer/ Counter 1 Timer/ Counter 0 External Interrupt 1 External Interrupt 0 RESET
PCALL AREA
TCALL AREA FFDFH FFE0H INTERRUPT VECTOR AREA FFFFH
Figure 8. Program Memory Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences execution of the service routine. The Table Call service locations are spaced at 2-byte interval : FFC0H for TCALL15, FFC2H for TCALL14, etc.
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Caution: Write only registers can not be accessed by bit manipulation instruction.
Data Memory
Figure 9 shows the internal Data Memory space available. Data Memory are divided into three groups, a user RAM, control registers and Stack.
Address
00H DATA MEMORY (RAM) 7FH 80H NOT USED BFH C0H FFH CONTROL REGISTERS 128 BYTES (INCLUDE STACK AREA)
Symbol R0 R0DD R4 R4DD R5 R5DD R6 R6DD PMR4 PMR5 BITR CKCTLR TM0 + Note 3 + Note 3 ADCM ADR BUR IENL IRQL IENH IRQH IEDS
R/W R/W W 1) R/W W 1) R/W W 1) R/W W 1) W 1) W 1) R W 1) R/W R/W R/W R/W 4) R W 1) R/W R/W R/W R/W W 1)
Power-on Reset Value
MSB LSB
Figure 9. Data Memory The stack pointer should be initialized within 00H to 7FH by software because of implemented area of internal data memory. The control registers are used by the CPU and Peripheral functions for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters, I/O ports. The control registers are in address C0H to FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detail informations of each register are explained in each peripheral sections.
C0H C1H C8H C9H CAH CBH CCH CDH D0H D1H D3H 2) D3H 2) E2H E4H E5H E8H E9H ECH F4H F5H F6H F7H F8H
X 00000000 X 00000000 X 000----X 0000----0-0--00 --0----00000000 ---10111 00000000 X X --000001 X X 0-0----0-0----00--00-00--00-00000000
Legend - = Unimplemented locations. X= Undefined value. NOTES: 1) The all write only registers can not be accessed by bit manipulation instruction. 2) The register BITR and CKCTLR are located at same address. Address D3H is read as BITR, as written to CKCTLR. 3) Several names are given at same address. Refer to below table.
Address E4H E5H T0 T1 When read Timer mode Capture Mode CDR0 CDR1 TDR0 TDR1 When write
4) Only bit 0 of ADCM can be read.
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GMS81504
Control Registers for the GMS81504
Address C0H C1H C8H C9H CAH CBH CCH CDH D0H D1H D3H1) D3H1) E2H E4H E5H E8H E9H ECH F4H F5H F6H F7H F8H R0 R0DD R4 R4DD R5 R5DD R6 R6DD PMR4 PMR5 BITR CKCTLR TM0 T0/ TDR0/ CDR0 T1/ TDR1/ CDR1 ADCM ADR BUR IENL IRQL IENH IRQH IEDS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R0 port data register R0 port direction register R4 port data register R4 port direction register R5 port data register R5 port direction register R6 port data register R6 port direction register CAP0 T1S T1ST BUZS T1SL1 EC0S ENPCK T1SL0 BTCL T0ST BTS2 T0CN INT1S BTS1 T0SL1 INT0S BTS0 T0SL0
Basic Interval Timer data register
Timer 0 register/ Timer data register 0/ Capture data register 0 Timer 1 register/ Timer data register 1/ Capture data register 1 BUCK1 AE AIF INT0E INT0IF BUCK0 INT1E INT1IF ADEN BU5 BITE BITIF ADS2 BU4 ADS1 BU3 T0E T0IF IED1H ADS0 BU2 T1E T1IF IED1L ADST BU1 IED0H ADSF BU0 IED0L ADC result data register
Legend - = Unimplemented locations. NOTES: 1) The register BITR and CKCTLR are located at same address. Address D3H is read as BITR, written to CKCTLR.
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GMS81504
HYUNDAI MicroElectronics R4 and R4DD registers: R4 is an 8-bit bidirectional I/O port (address C8H). Each pin is individually configurable as input and output through the R4DD register (address C9H). In addition, Port R4 is multiplexed with various special features. The control register PMR4 (address D0H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as External interrupt or External counter or Timer clock out, write "1" to the corresponding bit of PMR4.
Port Pin R40 R41 R44 Alternate Function INT0 (External Interrupt 0) INT1 (External Interrupt 1) EC0 (External Count Input to Timer/ Counter 0) T1O (Timer 1 Clock-Out)
I/O PORTS
The GMS81504/08 have five ports, R0, R1, R4, R5, R6. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ports are used as a general purpose input port. All pins have data direction registers which can configure these pins as output or input. A "1" in the port direction register configures the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of R1 as output ports and the odd numbered bits as input ports, write "55H" to address C1H (R0 direction register) during initial setting as shown in Figure 10.
WRITE "55H" TO PORT R0 DIRECTION REGISTER 01010101 C0H C1H : C8H C9H R0 DATA R0 DIRECTION : R4 DATA R4 DIRECTION 765 4321 0 BIT
R46
Regardless of the direction register R4DD, PMR4 is selected to use as alternate functions, port pin can be used as a corresponding alternate features.
IOIOIOIO 765 4321 0 PORT
Port 4 Data Register R4
ADDRESS: C8H RESET VALUE: Undefined
I: INPUT PORT O: OUTPUT PORT
R47 R46 R45 R44 R43 R42 R41 R40
Figure 10. Example port I/O assignment Reading data register reads the status of the pins whereas writing to it will write to the port latch. R0 and R0DD registers: R0 is a 8-bit bidirectional I/O port (address C0H). Each pin is individually configurable as input and output through the R0DD register (address C1H).
ADDRESS: C0H RESET VALUE: Undefined
Input/ Output data
Port 4 Direction Register R4DD
ADDRESS: C9H RESET VALUE: 00000000
R47 R46 R45 R44 R43 R42 R41 R40
Direction select 0: Input 1: Output
Port 0 Data Register R0
R07 R06 R05 R04 R03 R02 R01 R00
Input/ Output data
Port 0 Direction Register R0DD
ADDRESS: C1H RESET VALUE: 00000000
R07 R06 R05 R04 R03 R02 R01 R00
Direction select 0: Input 1: Output
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HYUNDAI MicroElectronics R5 and R5DD registers: R5 is a 3-bit bidirectional I/O port (address CAH). R55, R56 and R57 only are physically implemented on this device. R56, R57 have internal pullups which is activated on input but deactivated on output. As input, these pins that are externally pull low will source current (IP2 on the DC characteristics) because of the internal pullups.
Caution: Pins R56, R57 are served on 30SDIP package only, but not served on 28SOP . Refer to Pin assignment.
GMS81504
Port 5 Data Register R5
R55 -
ADDRESS: CAH RESET VALUE: Undefined R51 R50
Input/ Output data
Port 5 Direction Register R5DD
R55 -
ADDRESS: CBH RESET VALUE: --0---00 R51 R50
Each pin is individually configurable as input and output through the R5DD register (address CBH).
Port Pin R55 Alternate Function BUZ (Square-wave output for Buzzer driving) Port 5 Mode Register PMR5
BUZS -
Direction select 0: Input 1: Output
ADDRESS: D1H RESET VALUE: --0-----
The control register PMR5 (address D1H) controls the selection alternate function. After reset, this value is "0", port may be used as general I/O ports. To use buzzer function, write "1" to the PMR5.
0: R55 1: BUZ (Buzzer Port)
Port 4 Mode Register
MSB
ADDRESS: D0H RESET VALUE: -0-0--00 LSB
PMR4
-
T1S
-
EC0S
-
-
INT1S INT0S 0: R40 1: INT0 0: R41 1: INT1
0: R44 1: EC0 0: R46 1: T1O
Edge Selection Register
MSB
ADDRESS: F8H RESET VALUE: ----0000 LSB
IEDS
-
-
-
INT1 INT0
External Interrupt Edge select 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)
LSB
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GMS81504 R6 and R6DD registers: R6 is a 4-bit port (address CCH). Pins R64~R67 are individually configurable as input and output through the R6DD register (address CDH).
Port Pin R64 R65 R66 R67 Alternate Function AN4 (ADC input 4) AN5 (ADC input 5) AN6 (ADC input 6) AN7 (ADC input 7)
HYUNDAI MicroElectronics
Port 6 Data Register R6
R67 R66 R65 R64 -
ADDRESS: CCH RESET VALUE: Undefined -
Input/ Output data
Port 6 Direction Register R6DD
R67 R66 R65 R64 -
ADDRESS: CDH RESET VALUE: 0000----
R6DD (address CDH) controls the direction of the R6 pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs.
Direction select 0: Input 1: Output
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GMS81504 timer interrupt. The BITR is interrupt request flag of Basic interval timer.
Caution: All control bits of Basic interval timer are in CKCTLR register which is located at same address with BITR (address D3H). Address D3H is read as BITR, written to CKCTLR.
BASIC INTERVAL TIMER
The GMS81504 has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 11. The 8-bit Basic interval timer register (BITR) is incremented every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 16 to 2048, the count rate is 1/16 to 1/2048 of the oscillator frequency. As the count overflows from FFH to 00H, this overflow causes to generate the Basic interval
When write "1" to bit BTCL of CKCTLR, data register is cleared to "0" and restart to count-up. It becomes "0" after one machine cycle by hardware.
BTS[2:0]
BTCL CLEAR
XIN PIN
/16 /32 /64 /128 /256 /512 /1024 /2048
PRESCALER
3
8
MUX
BITR (8 BITS)
BITIF
BASIC INTERVAL TIMER INTERRUPT
Figure 11. Block Diagram of The Basic Interval Timer
CKCTLR Symbol
ENPCK BTCL
-
-
-
ENPCK BTCL
BTS2
BTS1
BTS0
ADDRESS: D3H RESET VALUE: ---10111
Position
CKCTLR.4 CKCTLR.3
Name and Significance
Enable Peripheral clock. 1: Supply clock to every peripherals 0: Stop clock BTCL is set to "1", BITR is cleared. BTCL becomes "0" automatically after one machine cycle, and starts counting.
BASIC INTERVAL TIMER CLOCK SELECTION BTS2 BTS1 BTS0 Prescale value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 16 32 64 128 256 512 1024 2048
Figure 12. CKCTLR: Control Clock Register
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GMS81504
HYUNDAI MicroElectronics In addition the "capture" function, the register is incremented in response external or internal clock sources same with timer or counter function. When external clock edge input, the count register is captured into Timer data register correspondingly. It has four operating modes: "8-bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit capture" which are selected by bit in Timer mode register TM0 as shown in right Table.
TM0 FOR TIMER 0, TIMER 1 CAP0 0 1 0 1
T1SL1 T1SL0
TIMER/COUNTER
The GMS81504 has two Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 are can be used either the two 8-bit Timer/Counter or one 16-bit Timer/Counter to combine them. In the "timer" function, the register is incremented every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 4 and most clock consists of 64 oscillator periods, the count rate is 1/4 to 1/64 of the oscillator frequency. In the "counter" function, the register is incremented in response to a 1-to-0 (falling edge) transition at its corresponding external input pin, EC0.
EX)
When TM0: 00110111 (PRESCALER= 16) TDR0: FAH = 250D OSCILLATOR FREQ.= 4MHz INTERRUPT PERIOD =
Timer 0 16-bit Capture 8-bit Timer 8-bit Capture
Timer 1
0 0 X X
0 0 X X
16-bit Timer/Counter 8-bit Timer 8-bit Timer
1 x 16 x 250 = 1ms 4 x 106 Hz COUNT PULSE PERIOD 4 us
MATCH (TDR0 = T0) TDR0
FA F9 F8 F7 F6 F5 F4 F3 F2 F1
3 1 00H CLEAR CLEAR CLEAR TIME 2
TIMER 0 INTERRUPT
OCCUR INTERRUPT INTERRUPT PERIOD
OCCUR INTERRUPT
OCCUR INTERRUPT
Figure 13. Timer Count Operation Example
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HYUNDAI MicroElectronics
GMS81504
TDR0
MATCH Stop Stop Clear and Start Restart
MATCH
Count Up
00H CLEAR CLEAR CLEAR TIME
TIMER INTERRUPT
OCCUR INTERRUPT
OCCUR INTERRUPT
HIGH TxST LOW HIGH TxCN LOW
Figure 14. Timer Count Operation
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GMS81504
HYUNDAI MicroElectronics In the Timer 0, timer register T0 increments from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit) As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx.
Caution: The contents of Timer data register TDRx should be initialized 1H~FFH except 0H, because it is undefined after reset.
8-bit Timer/Counter Mode
The GMS81504 has two 8-bit Timer/Counters, Timer 0, Timer 1. The Timer 0, Timer 1 only as shown in Figure 15. The "timer" or "counter" function is selected by control registers TM0 as shown in Figure 17. To use as an 8-bit timer/counter mode, bit CAP0 of TM0 should be cleared to "0" and bits T1SL1, T1SL0 of TM0 should not set to zero (Figure 15). These timers have each 8-bit count register and data register. The count register is incremented by every internal or external clock input. The internal clock has a prescaler divide ratio option of 4, 16, 64 (selected by control bits T1SL1, T1SL0 of register TM0).
In counter function, the counter is incremented every 1-to-0 (falling edge) transition of EC0 pin. In order to use counter function, the bit EC0S of the Port mode register PMR4 are set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not.
LSB
MSB
TM0
CAP0 0
T1ST X
T1SL1 T1SL0
T0ST X
T0CN X
T0SL1 T0SL0 X X
0
0
ADDRESS: E2H RESET VALUE: 00H
T0SL[1:0] EDGE DETECTOR EC0 PIN "1" XIN PIN
T0ST 0: Stop 1: Clear and Start "0" T0 (8-BITS) CLEAR
/4 / 16 / 64
PRESCALER
MUX T0CN T0IF COMPARATOR TIMER 0 INTERRUPT
TIMER 0
TDR0 (8-BITS)
T1SL[1:0]
T1ST 0: Stop 1: Clear and Start T1 (8-BITS) CLEAR
MUX
TIMER 1
COMPARATOR TDR1 (8-BITS)
T1IF
TIMER 1 INTERRUPT
F/F
T1O PIN
Figure 15. 8-bit Timer/Counter Mode
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HYUNDAI MicroElectronics To pulse out, the timer match can goes to port pin as shown in Figure 15. Thus, pulse out is generated by the timer match. These operation is implemented to pin T1O. The pin T1O is output from Timer 1. Output frequency is calculated as following equation.
fXIN 2 Prescaler TDR
GMS81504
fT1O (Hz) =
fT1O: Pin T1O output pulse frequency fXIN: Oscillator frequency Prescaler: Refer to bit T1SL1,T1SL0 of TM0 at Figure 17.
MSB
LSB T1S EC0S INT1S INT0S ADDRESS: D0H RESET VALUE: -0-0--00
PMR4
-
0: R40 1: INT0 (EXTERNAL INTERRUPT 0) 0: R41 1: INT1 (EXTERNAL INTERRUPT 1)
0: R44 1: EC0 (EXTERNAL INPUT PIN FOR TIMER 0) 0: R46 1: T1O (TIMER 1 PULSE OUTPUT)
Figure 16. PMR4: R4 Port Mode Register
MSB
LSB T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0 TIMER 0 T0ST When set, The Timer 0 Count Register is cleared and start again. When cleared, stop the counting. ADDRESS: E2H RESET VALUE: 00H
TM0
CAP0
TIMER 1 CAP0 Capture mode selection flag, When set, timer operate as one 16-bit capture timer combine two 8-bit timers. T1ST When set, Timer 1 count register is cleared and start again. When cleared, stop the counting.
T0CN Start/Stop control for Timer 0. A logic 1 starts the timer. TIMER 0
TIMER 1 T1SL1 0 0 1 1 T1SL0 INPUT CLOCK 0 1 0 1 16-BIT TIMER MODE (NOTE 1) 8-BIT TIMER, / 4 PRESCALER 8-BIT TIMER, / 16 8-BIT TIMER, / 64
T0SL1 0 0 1 1
T0SL0 INPUT CLOCK 0 1 0 1 Timer or Counter select / 4 PRESCALER / 16 / 64
NOTE: If this mode selected, the Timer 0 are used as a 16-bit timer mode. The Timer 1 is engaged to the Timer 0. The source clock is selected by bits T0SL1 and T0SL0.
Figure 17. TM0: Timer 0, Timer 1 Mode Register
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GMS81504
HYUNDAI MicroElectronics The clock source of the Timer 0 is selected either internal or external clock by bit T0SL1, T0SL0. Bit T1ST is not effect in this 16-bit mode. Bit T0SL1 and T0SL0 select the clock source among three prescaler divide ratio and external EC0 clock.
16-bit Timer/Counter Mode
The Timer register is being run with all 16 bits. A 16-bit timer/counter register T0, T1 are incremented from 0000H until it matches TDR0, TDR1 and then resets to 0000H. The match output generates Timer 0 interrupt.
MSB
LSB CAP0 0 T1ST X T1SL1 T1SL0 0 0 T0ST X T0CN X ADDRESS: E2H T0SL1 T0SL0 RESET VALUE: 00H X X
TM0
T0SL[1:0] EDGE DETECTOR
DO NOT CARE "0"
T0ST 0: Stop 1: Clear and Start T1 T0 (16 BITS) CLEAR
EC0 PIN
XIN PIN
/4 / 16 / 64
PRESCALER
MUX
"1" T0CN
T0IF
TIMER 0 + TIMER 1
TDR1 TDR0 (16 BITS) HIGHER LOWER
COMPARATOR
TIMER 0 INTERRUPT (NOT TIMER 1 INTERRUPT)
Figure 18. 16-bit Timer/Counter Mode
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HYUNDAI MicroElectronics
GMS81504 register T0, to be captured into registers CDR0, respectively. After captured, Timer 0 register T0 is cleared and restarts by hardware.
Caution: The CDRx and TDRx are in same address. In the capture mode, reading operation is read the CDRx, not TDRx because path is opened to the CDRx.
8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 as shown in Figure 19. In this mode, Timer 1 still operates as an 8-bit timer/counter. In 8-bit capture mode, Timer 1 can not be used as capture mode. The Timer/Counter register is incremented in response internal or external input. This counting function is same with normal timer mode, but Timer interrupt is not generated. Timer/Counter still does the above, but with the added feature that a edge transition at external input INT0 pin causes the current value in the Timer 0
It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INT0 pin generates an interrupt signal.
MSB
LSB T1ST X T0SL[1:0] T1SL1 T1SL0 T0ST X T0CN X T0SL1 X T0SL0 X ADDRESS: E2H RESET VALUE: 00H
TM0
CAP0 1
0
0
T0ST 0: Stop 1: Clear and Start 0 T0 (8-BITS)
EDGE DETECTOR EC0 PIN
XIN PIN
/4 / 16 / 64
PRESCALER
MUX
1 T0CN CAPTURE
TIMER 0
CDR0 (8-BITS)
INT0 PIN T1SL[1:0] 00 IEDS[1:0] MUX T1ST 0: Stop 1: Clear and Start T1 (8-BITS) CLEAR
INT0IF
INT0 INTERRUPT
TIMER 1
COMPARATOR TDR1 (8-BITS)
T1IF
TIMER 1 INTERRUPT
F/F
T1O PIN
Figure 19. 8-bit Capture Mode
31
GMS81504
HYUNDAI MicroElectronics Bit T1ST is not effect in this 16-bit mode. Bit T0SL1 and T0SL0 select the clock source among three prescaler divide ratio and external EC0 clock.
16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits.
MSB
DO NOT CARE T1ST X T1SL1 0 T1SL0 0 T0ST X T0CN X T0SL1 X
LSB T0SL0 X ADDRESS: E2H RESET VALUE: 00H
TM0
CAP0 1
T0SL[1:0] EDGE DETECTOR 0 EC0 PIN MUX 1 T0CN
T0ST 0: Stop 1: Clear and Start T1 (8-BITS) T0 (8-BITS)
XIN PIN
/4 / 16 / 64
PRESCALER
IEDS[1:0]
TIMER 0 + TIMER 1
CDR1 (8-BITS) HIGHER
CDR0 (8-BITS) LOWER INT0IF INT 0 INTERRUPT
INT0 PIN
Figure 20. 16-bit Capture Mode
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HYUNDAI MicroElectronics
GMS81504 use analog inputs, I/O is selected input mode by R6DD direction register.
ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AVDD of ladder resistance of A/D module. The A/D module has two registers which are the control register ADCM and A/D result register ADR. The register ADCM, shown in Figure 22, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. To
How to Use A/D Converter
The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag AIF is set. The block diagram of the A/D module is shown in Figure 21. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 40 uS (at fXIN=4 MHz).
ADEN "0" AVDD PIN "1"
LADDER RESISTOR DECODER
3 R64/AN4 R65/AN5 R66/AN6 R67/AN7 100 101
ADS[2:0] 000~011: RESERVED
VIN 110 111
S/H SAMPLE & HOLD
SUCCESSIVE APPROXIMATION CIRCUIT
AIF
A/D INTERRUPT
ADR INPUT CHANNEL SELECTION
ADDRESS: E9H RESET VALUE: Undefined
A/D RESULT REGISTER
Figure 21. A/D Block Diagram
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GMS81504
HYUNDAI MicroElectronics
MSB -
-
R/W ADEN
R/W ADS2
R/W ADS1
R/W ADS0
R/W ADST
LSB R ADSF ADDRESS: E8H RESET VALUE: --00001
ADCM
-
A/D status bit (READ ONLY) 0: A/D conversion is in process. 1: A/D conversion is completed, not in process. RESERVED A/D start bit 1: Setting this bit starts an A/D conversion. After one cycle, bit is cleared to "0". 0: Bit force to zero. Analog channel select 000~011: Reserved 100: channel 4 (R64/AN4) 101: channel 5 (R65/AN5) 110: channel 6 (R66/AN6) 111: channel 7 (R67/AN7) A/D converter Enable bit 0: A/D converter module shut off and consumes no operating current. 1: Enable A/D converter
Figure 22. ADCM: A/D Converter Control Register
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HYUNDAI MicroElectronics
GMS81504
BUZZER FUNCTION
The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (250 Hz~125 kHz at fXIN=4 MHz) by user programmable counter. Pin R55 is assigned for output port of Buzzer driver by setting the bit 5 of PMR5 (address D1H) to "1". At this time, the pin R55 must be defined as output mode (the bit 5 of R5DD=1). In the emulator, even if pin R55 is defined as input, buzzer output is available. The bit 0 to 5 of BUR determines output frequency for buzzer sound. Frequency calculation is following below. fBUZ (Hz) = fXIN 2 Prescaler ratio BUR value
/ 16 / 32 / 64 / 128
COUNTER (6 BIT)
MUX
XIN PIN
PRESCALER BUR[7:6] BUR[5:0] (6 BIT) BUR REGISTER
F/F BUZ PIN
Figure 23. Buzzer Driver clock from prescaler output. The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increment from 00H until it matches 6-bit register BUR.
Caution: The register BUR contains undefined value after reset. It must be initialized with 1H~3FH (none 0H).
fBUZ: Buzzer frequency fXIN: Oscillator frequency Prescaler: Prescaler divide ratio by BUCK1, BUCK0 BUR:Lower 6-bit of BUR. Buzzer period data value
The bits BUCK1, BUCK0 of BUR selects the source
MSB
LSB BU5 BU4 BU3 BU2 BU1 BU0 ADDRESS: ECH RESET VALUE: Undefined
BUR
BUCK1 BUCK0
Prescaler ratio 00: fXIN / 16 01: fXIN / 32 10: fXIN / 64 11: fXIN / 128
6-bit BUR value
Figure 24. BUR: Buzzer Period Data Register
MSB
LSB BUZS ADDRESS: D1H RESET VALUE: --0-----
PMR5
-
R55/ BUZ Port Selection 0: R55 1: BUZ
Figure 25. PMR5: Port 5 Mode Register
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GMS81504
HYUNDAI MicroElectronics The Timer 0, Timer 1 Interrupts are generated by T0IF, T1IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by AIF which is set by finishing the analog to digital conversion. The Basic Interval Timer Interrupt is generated by BITIF which are set by a overflow in the timer/counter register. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 27. These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
INTERRUPTS
The GMS81504 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, priority circuit and Master enable flag(I flag of PSW). The configuration of interrupt circuit is shown in Figure 1-26. 12 interrupt sources are provided including the Reset.
Interrupt source Hardware RESET External Interrupt 0 External Interrupt 1 Timer/Counter 0 Timer/Counter 1 AD Converter Basic interval timer Symbol RESET INT0IF INT1IF T0IF T1IF AIF BITIF Priority 1 2 3 4 5 6 7
*Vector addresses are shown in Program Memory section.
The External Interrupts INT0, INT1 can each be transition-activated, depending on interrupt edge selection register.
INTERRUPT REQUEST FLAG
INTERRUPT ENABLE FLAG
IRQH INT0 INT1 TIMER0 TIMER1 INT0IF BIT 7 INT1IF BIT 6 T0IF T1IF BIT 3 BIT 2
IENH 0 1
I-flag is in PSW, it is cleared by "DI", set by "EI" instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.
BRK (Software Interrupt)
PRIORITY CONTROL IENL BIT 7 BIT 5
0 1 I-FLAG Master Interrupt Enable Flag
RELEASE THE STOP (IF IN STOP MODE) TO CPU
IRQL ADC BIT * AIF BITIF
RESET
NOTE: * BIT: BASIC INTERVAL TIMER
Figure 1-26. Block Diagram of Interrupt Function
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HYUNDAI MicroElectronics
GMS81504
MSB
LSB T0E T1E ADDRESS: F6H RESET VALUE: 00--00--
IENH
INT0E INT1E
MSB
LSB BITE ADDRESS: F4H RESET VALUE: 0-0-----
IENL
AE
Enables or disables the interrupt individually. If flag is cleared, the interrupt is disabled. 0: Disable 1: Enable
Figure 27. IENH, IENL: Interrupt Enable Registers When an interrupt is responded to, the I-flag is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before reenabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and write. both edge. INT0, INT1 are multiplexed with general I/O ports (R40, R41). To use external interrupt pin, set bit 0 to bit 3 of the port mode register PMR4. The PMR4 and IEDS registers are shown in Figure 30.
EDGE DETECTOR IEDS[1:0] INT0 INT0IF INT0 INTERRUPT
External Interrupt
External interrupt on INT0, INT1 pins are edge triggered depending on the edge selection register IEDS. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, Figure 28. External Interrupt
IEDS[3:2] INT1 INT1IF INT1 INTERRUPT
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GMS81504
HYUNDAI MicroElectronics
MAX. 13 fOSC
8 fOSC
fXIN
INTERRUPT ACTIVE INSTRUCTION EXECUTION (INTERRUPT HOLDING) INTERRUPT PROCESSING INTERRUPT ROUTINE
Figure 29. INT Pin Interrupt Timing
MSB
LSB T1S EC0S INT1S INT0S ADDRESS: D0H RESET VALUE: -0-0--00
PMR4
-
0: R40 1: INT0 (EXTERNAL INTERRUPT 0) 0: R41 1: INT0 (EXTERNAL INTERRUPT 1)
0: R44 1: EC0 (EXTERNAL INPUT PIN FOR TIMER 0) 0: R46 1: T1O (TIMER 1 PULSE OUTPUT)
MSB
LSB IED1H IED1L IED0H IED0L INT1 INT0 ADDRESS: F8H RESET VALUE: ----0000
IEDS
-
Edge selection register IEDxH.IEDxL 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling)
Figure 30. PMR4 and IEDS Registers
38
HYUNDAI MicroElectronics
GMS81504
BRK Interrupt
Software interrupt can be invoked by BRK instruction, which is the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL0. Each processing step is determined by B-flag as shown below.
Multiple Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines by hardware which request is serviced. Hardware interrupt priority is shown in Page36. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user set I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress.
B-FLAG = 0 =1 BRK or TCALL0 BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE
In this example, the INT0 interrupt can be serviced without any pending, even TIMER 0 is in progress. Because of re-setting the interrupt enable registers IENH, IENL and master enable flag "EI" in the Timer/Counter 0 routine. TIMER 0 ROUTINE INT 0 ROUTINE MOV IENH,#80H MOV IENL,#00H EI
RET
MAIN ROUTINE
Occur TIMER 0 INTERRUPT
INT0 ROUTINE
Figure 31. Execution of BRK/ TCALL0
MOV IENH,#FFH MOV IENL,#FFH RETI
RETI
Figure 32. Execution of Multi-Interrupt
39
GMS81504
HYUNDAI MicroElectronics restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize (minimum 20 msec).
Caution: The NOP instruction have to be written more than two to next line of the STOP instruction. Ex) STOP NOP NOP
STOP MODE
For applications where power consumption is a critical factor, device provides reduced power of STOP. An instruction that STOP causes that to be the last instruction executed before going into the Stop mode. In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register Rx, port direction register RxDD. The status of peripherals during Stop mode is shown below.
Peripheral RAM Control registers I/O Oscillation XIN XOUT Status Retain Retain Retain Stop Low High
Release Stop Mode
The exit from Stop mode is hardware reset or external interrupt. Reset redefines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. When exit from Stop mode by external interrupt from Stop mode, enough oscillation stabilization time is required to normal operation. Figure 33 shows the timing diagram. When release the Stop mode, the
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. The reset should not be activated before VDD is
OSCILLATOR
INTERNAL CLOCK
EXTERNAL INTERRUPT
BASIC INTERVAL TIMER COUNTER
N
N+1
N+2 STOP INSTRUCTION EXECUTION
00
01
FE
FF
00
01
02
03
CLEAR BASIC INTERVAL TIMER
NORMAL OPERATION
STOP MODE
STABILIZATION TIME tST > 20 ms
NORMAL OPERATION
Figure 33. Timing of Stop Release by External Interrupt
40
HYUNDAI MicroElectronics
GMS81504
Wake-up and Reset Function Table
Event RESET STOP instruction External Interrupt External Interrupt Wake-up Chip Status before event Do not care Normal operation Normal operation Chip function after event PC Vector N+1 Vector Vector N+1 Oscillator Circuit on off on on on
Stop, I-flag = 1 Stop, I-flag = 0 PC: Program Counter contents after the event. N: Address of STOP instruction.
Basic interval timer is activated on wake-up. It is incremented from 00H until FFH then 00H. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time. This guarantees that crystal oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 34.
Minimizing Current Consumption in Stop Mode
The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Weak pull-ups on port pins should be turned off, if possible. All inputs should be either as VSS or at VDD (or as close to rail as possible). An intermediate voltage on an input pin causes the input buffer to draw a significant amount of current.
STOP MODE
OSCILLATOR
INTERNAL CLOCK
RESET tST = 64 ms at 8 MHz STABILIZATION TIME Time can not be control by software.
STOP INSTRUCTION EXECUTION
Figure 34. Timing of Stop Mode Release by Reset
41
GMS81504
HYUNDAI MicroElectronics
Register A X Y PSW PC SP R0 R0DD R4 R4DD R5 R5DD R6 R6DD PMR4 PMR5 BITR CKCTLR TM0 TDR0/ T0/ CDR0 TDR1/ T1/ CDR1 ADCM ADR BUR IENH IENL IRQH IRQL IEDS - = unimplemented bit X= unknown Content X X X 00H X X X 00000000 X 00000000 X 000----X 0000----0-0--00 --0----00H --010111 00H X X --000001 X X 00--00-0-0----00--00-0-0---------000
RESET
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 8 MHz) plus 7 oscillator periods are required to start execution as shown in Figure 36. Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Initial state of each register is as follow. Therefore, this RAM should be initialized before reading or testing it.
EX) 5V OPERATION +5V 10K RESET + 10uF 7042 4.2V RESET IC
Figure 35. Example of Reset circuit
1 OSCILLATOR
2
3
4
5
6
7
RESET
ADDRESS BUS
?
?
?
?
FFFE FFFF
Start
DATA BUS
?
?
?
?
FE
ADL
ADH
OP Code
tST = 64 ms at 8 MHz STABILIZATION TIME
RESET PROCESS STEP
MAIN PROGRAM
Figure 36. Timing Diagram after Reset 42
HYUNDAI MicroElectronics
GMS81504
OSCILLATOR CIRCUIT
XIN and XOUT are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 37.
C1 XOUT XOUT C2 RESET XIN VSS R00 R01
VSS XIN
Recommend: C1,C2 = 30 pF 10 pF for Crystals.
Figure 38. Layout of Crystal Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 38. for the layout of the crystal. In all cases, an external clock operation is available.
Figure 37. Oscillator Connections To drive the device from an external clock source, XOUT should be left unconnected while XIN is driven as shown in Figure 39. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed.
N/C EXTERNAL OSCILLATOR SIGNAL
XOUT XIN VSS
Figure 39. External Clock Drive Configuration
43
GMS81504
HYUNDAI MicroElectronics In assembler and file type, two files are generated after compiled. One is "*.HEX", another is "*.OTP". The "*.HEX" file is used for emulation in circuit emulator CHOICE-JrTM and "*.OTP" file is used for programming to OTP device.
OTP PROGRAMMING
The GMS81504T is one-time PROM (OTP) microcontroller with 4K bytes electrically programmable read only memory for the GMS81504 system evaluation, first production and fast mass production. To programming the OTP device, user can have two way. One is using the universal programmer which is support HME microcontrollers, other is using the general EPROM programmer.
Programming Procedure
1. Select the EPROM device and manufacturer on EPROM programmer (Intel 27C256) 2. Select the programming algorithm as a Intelligent mode (apply 1ms writing pulse). 3. Load the file (*.OTP) to the programmer. 4. Set the programming address range as below table.
Address Buffer start address Buffer end address Device start address Set Value 7000H 7FFFH 7000H
1. Using the Universal programmer
Third party universal programmer are shown as below.
Manufacturer: Advantech Web site: http://www.aec.com.tw Programmer: LabTool-48 Manufacturer: Hi-Lo systems Web site: http://www.hilosystems.com.tw Programmer: ALL-11, GANG-08
Socket adapters are supported from third party programmer manufacturer.
2. Using the general EPROM(27C256) programmer
When user use general EPROM programmer, socket adaper is essencially necessary. It convert pin to fit the pin of general 27C256 EPROM. Socket Adapter: OA815A-30SD (30SDIP)
5. Mount the socket adapter with the OTP device onto the PROM programmer. 6. Start the PROM programmer to programming/ verifying.
44
GMS81504T PROGRAMMING MANUAL
HYUNDAI MicroElectronics
GMS81504T PROGRAMMING SPECIFICATION
DEVICE OVERVIEW
The GMS81504T is a high-performance CMOS 8-bit microcontroller with 4K bytes of EPROM. The device is one of GMS800 family. The HYUNDAI GMS81504T is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS81504T provides the following standard features: 4K bytes of EPROM, 128 bytes of RAM, 23 I/O lines, 16-bit or 8-bit timer/counter, a precision analog to digital converter, on-chip oscillator and clock circuitry.
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MCU Mode R01 R00 R47 R46 R45 R44 R67/AN7 R66/AN6 AVREF R65/AN5 R64/AN4 R41/INT1 R40/INT0 R55/BUZ R56 I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O OTP Mode O1 O0 A0 A1 CE OE A2 A3 (1) A4 (1) A5 A6 A7 A8 I/O I/O I I I I I I I I I I I I I Pin No. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MCU Mode R57 RESET XIN XOUT VSS R43 R42 TEST R07 R06 R05 R04 R03 R02 V DD I/O I I O VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD OTP Mode A9 (1) (1) (2) VSS A10 A11 VPP O7 O6 O5 O4 O3 O2 VDD I I I O VSS I I VPP I/O I/O I/O I/O I/O I/O VDD
NOTES: 1. Check marked pins must be connected on VSS, because these pins are input ports during programming, program verify and reading 2. XOUT pin must be opened during programming.
I/O: Input/Output Pin I: Input Pin O: Output Pin
1
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
PIN FUNCTION (OTP Mode)
VPP (Program Voltage) VPP is the input for the program voltage for programming the EPROM. CE ( Chip Enable) CE is the input for programming and verifying internal EPROM. OE (Output Enable) OE is the input of data output control signal for verify. A0~A11 (Address Bus) A0~A11 are address input pins for internal EPROM. O0~O7 (EPROM Data Bus) These are data bus for internal EPROM. Pin connection during programming
PROGRAMMING
The GMS81504T has address A0~A11 pins. Therefore, the programmer just program 4K bytes data (address 7000H to 7FFFH) into the GMS81504T OTP device. During the programming, addresses A12~A15 of the programmer must be pulled to a logic high. When the programmer write the data from 7000H to 7FFFH, consequently, the data actually will be written into addresses F000H to FFFFHof the OTP device. 1. The data format to be programmed is made up of Motorola S1 format. Ex) "Motorola S1" format;
S0080000574154434880 S1247000E1FF3BFF04A13F8F06E101711B821B1BE01D1B3B191BF6181BF01C1BFF081BFF0AB0 S12470211BF5091BFF0B1BFF3F1B003E1B003D1B003C1BFF3B1B003A1BFF391BFF381BFF350D : : S1057FF2983FB2 S1057FFEFF0F6F S9030000FC
2. Down load above data into programmer from PC. 3. Programming the data from address 7000H to 7FFFH into OTP MCU, the data must be turned over respectively, and then record the data.When read the data, it also must be turned over. Ex) 00(00000000)FF(11111111), 76(01110110)89(10001001), FF(11111111)00(00000000) etc. 4. Of course, the check sum is result of the sum of whole data from address 7000H to 7FFFH in the file (not reverse
2
HYUNDAI MicroElectronics data of theOTP MCU).
GMS81504T PROGRAMMING SPECIFICATION
* When GMS81504T shipped, the blank data of it is initially 00H (not FFH). Programming Flow
Buffer Start Address:7000H Buffer End Address: 7FFFH Device Start Address: F000H xxxxxxxx.OTP
GMS81504T
Address F000H Program Verify Reading Universal Programmer
Address 7000H
Program area 4 K BYTES
Down Loading
File Type: Motorola S-format
FFFFH
7FFFH
Programming Example
GMS81504T device
Programmer Buffer Data E1 FF 3B FF 04 A1 3F 8F : : : : 98 3F : FF 0F Address 7000H 7001H 7002H 7003H 7004H 7005H 7006H 7007H : : : : 7FF2H 7FF3H : 7FFEH 7FFFH
File xxxxxxxx.OTP Data E1 FF 3B FF 04 A1 3F 8F : : : : 98 3F : FF 0F Address 7000H 7001H 7002H 7003H 7004H 7005H 7006H 7007H : : : : 7FF2H 7FF3H : 7FFEH 7FFFH
Data 1E 00 C4 00 FC 5E C0 70 : : : : 67 C0 : 00 F0
Address F000H F001H F002H F003H F004H F005H F006H F007H : : : : FFF2H FFF3H : FFFEH FFFFH
Program
Down Loading
Reading Verify
Up Loading
Checksum = E1+FF+3B+FF+04+A1+3F+8F+ + 98+3F+ +FF+0F
3
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
DEVICE OPERATION MODE
(TA = 25C 5C)
Mode Read Output Disable Programming Program Verify CE X VIH VIL X VIH VIH OE A0~A11 X X X X VPP VDD VDD VPP VPP VDD 5.0V 5.0V VDD VDD O0~O7 DOUT Hi-Z DIN DOUT
NOTES: 1. X = Either VIL or VIH 2. See DC Characteristics Table for VDD and VPP voltages during programming.
DC CHARACTERISTICS
(VSS=0 V, TA = 25C 5C)
Symbol VPP Item Intelligent Programming Quick-pulse Programming VDD(1) IPP (2) IDD (2) VIH VIL VOH VOL IIL
NOTES: 1. VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. The maximum current value is with outputs O0 to O7 unloaded.
Min 12.0 12.5 5.75 6.0
Typ -
Max 13.0 13.0 6.25 6.5 50 30
Unit V V V V mA mA V
Test condition
Intelligent Programming Quick-pulse Programming VPP supply current VDD supply current Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current
CE=VIL
0.8 VDD 0.2 VDD V DD-1.0 0.4 5
V V V uA IOH = -2.5 mA IOL = 2.1 mA
4
HYUNDAI MicroElectronics
GMS81504T PROGRAMMING SPECIFICATION
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be steady OUTPUTS Will be steady
May change from H to L May change from L to H Do not care any change permitted Does not apply
Will be changing from H to L Will be changing from L to H Changing state unknown Center line is high impedance "Off" state
READING WAVEFORMS
VIH
Addresses
VIL
Address Valid
VIH
(2)
OE
VIL
tAS
tOE tDH
VIH
Output
VIL
High-Z
Valid Output
NOTES: 1. The input timing reference level is 1.0 V for a VIL and 4.0V for a VIH at VDD=5.0V 2. To read the output data, transition requires on the OE from the high to the low after address setup time tAS.
5
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
PROGRAMMING ALGORITHM WAVEFORMS
Program Verify
Program
VIH
Addresses
VIL
Address Stable
tAS
VIH
tAH
Data In Stable High-Z Data out Valid
Data
VIL
tDS
12.5V
tDH
tDFP
VPP
VDD 6.0V
tVPS
VDD
5.0V VIH
tVDS
CE
VIL
tPW
VIH
tOES tOE
OE
VIL
tOPW
NOTES: 1. The input timing reference level is 1.0 V for a VIL and 4.0V for a VIH at VDD=5.0V
6
HYUNDAI MicroElectronics
GMS81504T PROGRAMMING SPECIFICATION
AC READING CHARACTERISTICS
(VSS=0 V, TA = 25C 5C)
Symbol tAS tOE tDH
NOTES: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.
Item Address setup time Data output delay time Data hold time
Min 2
Typ
Max
Unit us
Test condition
200 0
ns ns
AC PROGRAMMING CHARACTERISTICS
(VSS=0 V, TA = 25C 5C; See DC Characteristics Table for VDD and VPP voltages.)
Symbol tAS tOES tDS tAH tDH tDFP tVPS tVDS tPW tOPW tOE Item Address set-up time OE set-up time Data setup time Address hold time Data hold time Output disable delay time VPP setup time VDD setup time Program pulse width CE pulse width when over programming Data output delay time
. . . . . . . . . . . . . . . . 20 ns 0.45V to 4.55V 1.0V to 4.0V 1.0V to 4.0V
Min 2 2 2 0 1 0 2 2 0.95 2.85
Typ
Max
Unit us us us us us us us us
Condition* (Note 1)
1.0
1.05 78.75 200
ms ms ns (Note 2)
*AC CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%) Input Pulse Levels . . . . . . . . . . . Input Timing Reference Level . . . . . Output Timing Reference Level . . . . NOTES:
1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X (Intelligent Programming Algorithm only). Refer to page 8.
7
GMS81504T PROGRAMMING SPECIFICATION
HYUNDAI MicroElectronics
Intelligent Programming Algorithm
START
ADDRESS= FIRST LOCATION
VCC = 6.0V VPP = 12.5V
X=0
PROGRAM ONE 1 ms PULSE
INCREMENT X
X = 25 ? NO FAIL VERIFY ONE BYTE PASS
YES
VERIFY BYTE PASS
FAIL
PROGRAM ONE PULSE OF 3X msec DURATION
INCREMENT ADDRESS
NO
LAST ADDRESS ? YES VCC = VPP = 5.0V
COMPARE ALL BYTES TO ORIGINAL DATA PASS DEVICE PASSED
FAIL
DEVICE FAILED
8
MASK ORDER & VERIFICATION SHEET
GMS81504-HB
Customer should write inside thick line box. 1. Customer Information Company Name Application
YYYY MM DD
2. Device Information
Package Mask Data Hitel File Name Check Sum 30SDIP Chollian 28SOP Internet .OTP
Order Date Tel: Name & Signature: Fax:
(
0 00 0 h
)
27256
S et "F F h " in th is a re a 6F F F h 7 00 0 h 7F F F h
( 4K ) .O T P file da ta
(Please check mark into
)
3. Marking Specification
Customer's logo
HME GMS81504-HBxxx YYWW KOREA
GMS81504-HBxxx KOREA YYWW
Customer logo is not required Customer's part number HME ROM code number
Note: If the customer logo must be used in the special mark Please submit a clean original of the logo.
4. Delivery Schedule Date Customer Sample Risk Order
YYYY YYYY MM MM DD DD
Quantity pcs pcs
HME Confirmation
5. ROM Code Verification Verification D ate:
YYYY MM DD
This box is written after "5.Verification".
YYYY MM DD
Approval Date:
I agree w ith your verification data and confirm you to m ake m ask set.
Please confirm our verification data.
Check Sum: Tel: Name & Signature: Fax:
Tel: Name & Signature:
Fax:
HYUNDAI MicroElectronics

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